1. Technical Field
The present invention relates to digital clock generation, and more specifically, to generating a digital clock signal from a Differential Comparator Circuit which correctly handles a special case called the “high-high” condition.
2. Related Art
On a Front Side Bus, there are receiving circuits that convert small signal differential clock signals to a digital clock signal to be used on-chip. The inputs to these circuits are called the Strobe and StrobeN. A condition exists when a transmitting device stops driving the Front Side Bus (called bus change-over) and both Strobe and StrobeN signals are at logic ‘1’. During this condition, it is advantageous for the on-chip digital clock signal to remain in a well defined logic state despite the state of the signals coming in from the bus. Therefore, there is a need for a clock generation circuit (and a method for operating the same) in which the digital clock signal can be controlled to stay at a defined logic state.